1 mm pitch orthogonal BGAs currently represent the workhorse of most high complexity electronic designs. When these designs call for edge coupled differential signal traces to be routed from or through the pin fields of these 1 mm pitch BGA, space constraints and manufacturing limitations conspire to create a very challenging printed circuit board (PCB). When coupled with thicknesses in excess of 0.100″ (as is becoming routine), the capability to repeatably fabricate reliable product deteriorates rapidly. Challenges associated with this situation are well known in the industry.
The problem is to provide a method of routing two or more traces through two rows of through-hole (through-board) vias spaced apart at a standard BGA grid pitch (1 mm), using standard circuit card manufacturing techniques for a low-cost/low-risk solution.
Providing higher density routing within a BGA grid has been addressed in the prior art as follows:    1. U.S. application (Publication No. US2003/0183419) Ball Assignment for Ball Grid Array package: discloses sharing vias between rows of adjacent power (or ground) contact pads, thereby allowing vias which would normally be used to be omitted from the grid, which leaves additional room for routing tracks through the grid. A limitation of this technique is that it can be applied to only power and ground contacts, which limits the location and size of the additional routing room created. Another limitation is that it decreases the number of independent path to ground/power, thereby impacting electrical performance.    2. Another technique of increasing the room to route traces between rows of through-hole vias arranged to accommodate a BGA packaged device has been to minimize the via dimensions. This approach involves reducing the via and via pad diameters to allow more room for traces between adjacent vias. However, this alteration increases the via aspect ratio (AR=card thickness/via diameter) and the probability of “breakout” (where the via is not entirely contained within its capture pad as intended). Both of these effects decrease PCB manufacturability and via reliability. (The resulting vias have shown themselves to be more susceptible to failure at solder reflow during assembly because of expansion of high temperature, and to failure in the field due to thermal cycling.)    3. Techniques using composite circuit boards and blind vias can be used to increase the routing density in the BGA grid area, but these are costly approaches that it would be desirable to avoid.